United States Contract 1 week ago

Job Description:

Building a test bench for a block using System Verilog and UVM

Writing random tests, directed tests, error tests & performance tests for a block of Verilog and UVM.

Developing, maintaining and supporting of the UVM verification environment.

Debugging tests with design engineers to deliver functionally correct design blocks

writing & analyzing functional coverage, assertions

Generating and analyzing code coverage & writing waivers.

Job Type: Contract

Pay: $75.00 - $80.00 per hour


  • On call

Work Location: Remote

  • Company:
  • Job Type:
  • Posting Date:
    13th May 2022
  • Valid through:
    13th Jun 2022
  • Location:
  • Est. Salary:
    $75-80 / HOUR
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